The present invention relates to a semiconductor memory device such as a static random access memory (SRAM).
An SRAM, which is one type of semiconductor memory device, does not need refreshing. Therefore, the SRAM enables the system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for portable devices such as portable telephones.
There has been a demand for miniaturization of portable devices. To deal with this demand, the memory cell size of the SRAM must be reduced.
An objective of certain embodiments of the present invention is to provide a semiconductor memory device having memory cells of a reduced size.
According to one embodiment of the present invention, there is provided a semiconductor memory device comprising:
a memory cell which includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein:
the memory cell has first and second gate electrode layers, first and second drain-drain connecting layers, first and second drain-gate connecting layers, and a source contact layer;
the first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor;
the second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor;
a source region of the first and second driver transistors is located in a region between the first and second gate electrode layers;
the source contact layer is located in the region between the first and second gate electrode layers;
the first and second drain-drain connecting layers are located higher than the first and second gate electrode layers;
the first and second gate electrode layers are located between the first and second drain-drain connecting layers;
the first drain-drain connecting layer connects a drain region of the first driver transistor to a drain region of the first load transistor;
the second drain-drain connecting layer connects a drain region of the second driver transistor to a drain region of the second load transistor;
the first and second drain-gate connecting layers are located higher than the first and second gate electrode layers;
the first and second drain-gate connecting layers are located in a different layer from the first and second drain-drain connecting layers;
the first drain-gate connecting layer connects the first drain-drain connecting layer to the second gate electrode layer; and
the second drain-gate connecting layer connects the second drain-drain connecting layer to the first gate electrode layer.
The semiconductor memory device according to this embodiment of the present invention includes the gate electrode layers which become gates of inverters, the drain-drain connecting layers for connecting drains of the inverters, and the drain-gate connecting layers for connecting the gate of one inverter to the drain of the other inverter. In this semiconductor memory device, a flip-flop is formed of three layers (gate electrode layer, drain-drain connecting layer, and drain-gate connecting layer). Therefore, the pattern of each layer can be simplified (linear pattern, for example) in comparison with the case of forming a flip-flop of two layers. According to this semiconductor memory device, since the pattern of each layer can be thus simplified, a semiconductor memory device with a memory cell size of 4.5 xcexcm2 or less can be fabricated, for example.
According to this semiconductor memory device, the first gate and second gate electrode layers are located between the first drain-drain connecting layer and the second drain-drain connecting layer. Therefore, the source contact layer of the driver transistors can be disposed at the center of the memory cell. Moreover, a wiring layer which is formed in the same layer as the drain-drain connecting layer and to which the source contact layer is connected can be disposed at the center of the memory cell. This increases the degree of freedom relating to the formation of the first and second drain-gate connecting layers, whereby the memory cell size can be reduced. In the present invention, the source contact layer is a conductive layer used to connect the source region of the driver transistor to the wiring layer.
According to this semiconductor memory device, the drain-gate connecting layers are located higher than the gate electrode layers and the drain-drain connecting layers. Therefore, the source contact layer can be located in the region between gate electrode layers (or region between the first gate electrode layer and second gate electrode layer) while preventing the drain-gate connecting layer from coming in contact with the source contact layer. Therefore, parasitic resistance of the driver transistors can be decreased. Moreover, the pattern of the source region can be simplified (for example, a pattern with a uniform width such as an approximately linear pattern or rectangular pattern), whereby reproducibility of the pattern of the source region can be improved in a photolithography process. This increases dimensional accuracy of the channel width of the driver transistors, whereby the operation of the memory cell can be stabilized.
In this semiconductor memory device, the width of the source region may be approximately uniform.
The source contact layer may be located in the source region.
This semiconductor memory device may further comprise a word line, wherein: the word line is located on the side of the first and second driver transistors; the word line includes gate electrodes of the first and second transfer transistors; and the word line has a linear pattern.
According to this configuration, since the pattern of the word line is linear, the length of the word line can be decreased in comparison with a word line having a partly curved pattern. Therefore, according to this configuration, the resistance of the word line can be decreased. The width of a word line having a partly curved pattern tends to be decreased at the curved section. This causes the narrow line effect of silicide to occur in a salicide of the word line, whereby the resistance of the word line locally increases. According to this configuration, since the pattern of the word line is linear and does not have a curved section, occurrence of the narrow line effect of silicide caused by the curved section can be prevented, thereby preventing a local increase in the resistance of the word line due to the narrow line effect of silicide.
This semiconductor memory device may further comprise:
another memory cell which includes a third transfer transistor and a fourth transfer transistor;
first and second bit lines;
another word line; and
a well contact region, wherein:
the other memory cell is located adjacent to the memory cell;
the first and third transfer transistors use in common a first source/drain region to which the first bit line is connected;
the second and fourth transfer transistors use in common a second source/drain region to which the second bit line is connected;
the other word line includes gate electrodes of the third and fourth transfer transistors;
the other word line has a linear pattern;
the well contact region is located between the word line and the other word line; and
the memory cell and the other memory cell uses in common the well contact region.
According to this configuration, since the above word line and the other word line have a linear pattern, the well contact region can be located between the above word line and the other word line without increasing the memory cell area. Therefore, the size of the semiconductor memory device can be reduced.
According to this configuration, occurrence of latchup in the semiconductor memory device can be prevented. The reasons therefor are described below. Generally, when drain current flows by operating a transistor, substrate current (current from end section of drain to well contact region) flows. In particular, a large amount of substrate current flows in a driver transistor of which a word line is selected. An increase in the electric potential equivalent to the product of the substrate current and substrate resistance (well resistance) causes latchup to occur. According to this configuration, however, the well contact region can be disposed in the memory cell as well as in the well in which the driver transistors and the transfer transistors are formed. Moreover, the well contact region can be disposed in every memory cell in the direction of the word line. Therefore, the driver transistors and the well contact region can be located close together, whereby the substrate resistance can be decreased. Because of this, according to this configuration, occurrence of latchup can be prevented. In addition, the well contact region is preferably p-type.
In this semiconductor memory device, the word line may be located between the source region and the well contact region.
This semiconductor memory device may further comprise a contact pad layer, wherein:
the contact pad layer is used to connect the well contact region and the source region of the first and second driver transistors to a ground line; and
the contact pad layer is located in the same layer as the first and second drain-drain connecting layers.
According to this configuration, since a plurality of contacts can be disposed from the contact pad layer to the ground line, the parasitic resistance of the source region can be reduced. According to this configuration, the first and second gate electrode layers are located between the first drain-drain connecting layer and the second drain-drain connecting layer, and the contact pad layer is located between the first gate electrode layer and the second gate electrode layer. The contact pad layer and each gate electrode layer have a relation in which one is the upper layer and the other is the lower layer. Therefore, the contact pad layer can be disposed in the same layer as the drain-drain connecting layers without increasing the memory cell size. According to this configuration, the memory cell and the other memory cell can use in common the contact pad layer having a linear pattern.
In this semiconductor memory device, the first and second driver transistors may be n-type;
the first and second load transistors may be p-type;
the first and second transfer transistors may be n-type;
the memory cell may include first, second, third and fourth conductive layers;
the first and second gate electrode layers and a sub-word line may be located in the first conductive layer;
the first and second drain-drain connecting layers, a power supply line, and first, second and third contact pad layers may be located in the second conductive layer;
the first and second drain-gate connecting layers, a main-word line, and fourth, fifth and sixth contact pad layers may be located in the third conductive layer;
first and second bit lines and a ground line may be located in the fourth conductive layer;
the sub-word line may extend in a first direction;
the power supply line may be connected to source regions of the first and second load transistors;
the first contact pad layer may be used to connect the first bit line to a source/drain region of the first transfer transistor;
the second contact pad layer may be used to connect the second bit line to a source/drain region of the second transfer transistor;
the third contact pad layer may be used to connect the source region of the first and second driver transistors to the ground line;
the main-word line may extend in the first direction;
the fourth contact pad layer may be used to connect the first bit line to the source/drain region of the first transfer transistor;
the fifth contact pad layer may be used to connect the second bit line to the source/drain region of the second transfer transistor;
the sixth contact pad layer may be used to connect the source region of the first and second driver transistors to the ground line; and
the first and second bit lines may extend in a second direction which is perpendicular to the first direction.
According to this configuration, various properties (such as miniaturization, reliability, stability, and speed) required for semiconductor memory devices can be well-balanced and improved.
This semiconductor memory device may further comprise a plurality of the memory cells, a plurality of well contact regions of a primary conductivity type, and a plurality of well contact regions of a secondary conductivity type;
wherein each of the well contact regions of the primary conductivity type may be provided for a group of a predetermined number of memory cells arrayed in a first direction among the plurality of the memory cells; and
wherein each of the well contact regions of the secondary conductivity type may be provided for a group of two of the memory cells arrayed in a second direction which is perpendicular to the first direction.
In this configuration, the well contact region of the secondary conductivity type can be provided for every two memory cells arrayed in the second direction. This is because the source contact layer can be located in the region between gate electrode layers as described above, thereby creating an areal margin near the boundary between the adjoining memory cells. Note that the predetermined number of memory cells may be 32 or 64, for example.
In this configuration, the primary conductivity type may be n-type and the secondary conductivity type may be p-type. According to this configuration, the well contact region of the well on which an n-type transistor is formed becomes p-type, and the well contact region of the well on which a p-type transistor is formed becomes n-type. This improves the latchup prevention effect. The reasons therefor are described below.
An increase in the electric potential equivalent to the product of the substrate current and the substrate resistance (well resistance) causes latchup to occur. Generally, the amount of the substrate current is greater in the n-type transistor than in the p-type transistor. For example, when the substrate current in the n-type transistor is 1xc3x9710xe2x88x926A/xcexcm, the substrate current in the p-type transistor can be 1xc3x9710xe2x88x929A/xcexcm, which is three digits smaller. The substrate resistance (well resistance) increases as the distance between the memory cell and the well contact region increases.
In this configuration, since the p-type well contact region is disposed in every two memory cells, the memory cell is located relatively close to the well contact region. Therefore, the substrate resistance (well resistance) can be relatively reduced. This ensures that the substrate resistance (well resistance) is relatively small even if the substrate current in the n-type transistor is relatively large, thereby preventing the product of the substrate current and the substrate resistance (well resistance) from increasing.
Since each n-type well contact region is provided for a group of a predetermined number (32, for example) of memory cells, some memory cells are located at a relatively long distance from the well contact region. Therefore, the substrate resistance (well resistance) relatively increases. However, since the substrate current in the p-type transistor is relatively small, the product of the substrate current and the substrate resistance (well resistance) can be prevented from increasing even if the substrate resistance (well resistance) is relatively large. These are reasons for improvement in the latchup prevention effect.
According to this configuration, the p-type well contact region can be connected to the ground line in the memory cell. This eliminates the need for a ground line used only for the p-type well contact region, whereby the size of the semiconductor memory device can be reduced.
In this semiconductor memory device, each of the first and second gate electrode layers and the first and second drain-drain connecting layers may have a linear pattern; and the first and second gate electrode layers and the first and second drain-drain connecting layers may be parallel to each other.
According to this configuration, since the pattern of each layer is simple, a semiconductor memory device with a minute memory cell size can be fabricated.